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60 lines
2.7 KiB
Plaintext
60 lines
2.7 KiB
Plaintext
// This file is part of www.nand2tetris.org
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// and the book "The Elements of Computing Systems"
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// by Nisan and Schocken, MIT Press.
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// File name: projects/5/CPU.hdl
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/**
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* The Hack Central Processing unit (CPU).
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* Parses the binary code in the instruction input and executes it according to the
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* Hack machine language specification. In the case of a C-instruction, computes the
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* function specified by the instruction. If the instruction specifies to read a memory
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* value, the inM input is expected to contain this value. If the instruction specifies
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* to write a value to the memory, sets the outM output to this value, sets the addressM
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* output to the target address, and asserts the writeM output (when writeM = 0, any
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* value may appear in outM).
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* If the reset input is 0, computes the address of the next instruction and sets the
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* pc output to that value. If the reset input is 1, sets pc to 0.
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* Note: The outM and writeM outputs are combinational: they are affected by the
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* instruction's execution during the current cycle. The addressM and pc outputs are
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* clocked: although they are affected by the instruction's execution, they commit to
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* their new values only in the next cycle.
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*/
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CHIP CPU {
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IN inM[16], // M value input (M = contents of RAM[A])
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instruction[16], // Instruction for execution
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reset; // Signals whether to re-start the current
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// program (reset==1) or continue executing
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// the current program (reset==0).
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OUT outM[16], // M value output
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writeM, // Write to M?
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addressM[15], // Address in data memory (of M)
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pc[15]; // address of next instruction
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PARTS:
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Not(in=instruction[15], out=ai);
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Not(in=ai, out=ci);
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And(a=ci, b=instruction[5], out=wa);
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Mux16(a=instruction, b=alu, sel=wa, out=a);
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Or(a=ai, b=wa, out=la);
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ARegister(in=a, load=la, out=ao);
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Mux16(a=ao, b=inM, sel=instruction[12], out=am);
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And(a=ci, b=instruction[4], out=ld);
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DRegister(in=alu, load=ld, out=do);
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ALU(x=do, y=am, zx=instruction[11], nx=instruction[10],
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zy=instruction[9], ny=instruction[8], f=instruction[7],
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no=instruction[6], out=alu, zr=zr, ng=ng);
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Or16(a=false, b=ao, out[0..14]=addressM);
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Or16(a=false, b=alu, out=outM);
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And(a=ci, b=instruction[3], out=writeM);
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And(a=zr, b=instruction[1], out=jeq);
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And(a=ng, b=instruction[2], out=jlt);
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Or(a=zr, b=ng, out=zon);
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Not(in=zon, out=p);
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And(a=p, b=instruction[0], out=jgt);
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Or(a=jeq, b=jlt, out=jle);
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Or(a=jle, b=jgt, out=j);
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And(a=ci, b=j, out=l);
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Not(in=l, out=i);
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PC(in=ao, inc=i, load=l, reset=reset, out[0..14]=pc);
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} |