Complete project 3

Assignments/3_Sequential_Logic/Bit.hdl

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+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/3/a/Bit.hdl
+/**
+ * 1-bit register:
+ * If load is asserted, the register's value is set to in;
+ * Otherwise, the register maintains its current value:
+ * if (load(t)) out(t+1) = in(t), else out(t+1) = out(t)
+ */
+CHIP Bit {
+    IN in, load;
+    OUT out;
+
+    PARTS:
+    Mux(a=r, b=in, sel=load, out=i);
+    DFF(in=i, out=r, out=out);
+}

Assignments/3_Sequential_Logic/PC.hdl

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+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/3/a/PC.hdl
+/**
+ * A 16-bit counter.
+ * if      reset(t): out(t+1) = 0
+ * else if load(t):  out(t+1) = in(t)
+ * else if inc(t):   out(t+1) = out(t) + 1
+ * else              out(t+1) = out(t)
+ */
+CHIP PC {
+    IN in[16], reset, load, inc;
+    OUT out[16];
+    
+    PARTS:
+	Inc16(in=r, out=i);
+    Mux16(a=r, b=i, sel=inc, out=oi);
+    Mux16(a=oi, b=in, sel=load, out=ol);
+    Mux16(a=ol, b=false, sel=reset, out=or);
+    Register(in=or, load=true, out=r, out=out);
+}

Assignments/3_Sequential_Logic/RAM16K.hdl

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+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/3/b/RAM16K.hdl
+/**
+ * Memory of 16K 16-bit registers.
+ * If load is asserted, the value of the register selected by
+ * address is set to in; Otherwise, the value does not change.
+ * The value of the selected register is emitted by out.
+ */
+CHIP RAM16K {
+    IN in[16], load, address[14];
+    OUT out[16];
+
+    PARTS:
+    DMux4Way(in=load, sel=address[0..1], a=x1, b=x2, c=x3, d=x4);
+    RAM4K(in=in, out=y1, load=x1, address=address[2..13]);
+    RAM4K(in=in, out=y2, load=x2, address=address[2..13]);
+    RAM4K(in=in, out=y3, load=x3, address=address[2..13]);
+    RAM4K(in=in, out=y4, load=x4, address=address[2..13]);
+    Mux4Way16(a=y1, b=y2, c=y3, d=y4, sel=address[0..1], out=out);
+}

Assignments/3_Sequential_Logic/RAM4K.hdl

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+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/3/b/RAM4K.hdl
+/**
+ * Memory of 4K 16-bit registers.
+ * If load is asserted, the value of the register selected by
+ * address is set to in; Otherwise, the value does not change.
+ * The value of the selected register is emitted by out.
+ */
+CHIP RAM4K {
+    IN in[16], load, address[12];
+    OUT out[16];
+
+    PARTS:
+    DMux8Way(in=load, sel=address[0..2], a=x1, b=x2, c=x3, d=x4, e=x5, f=x6, g=x7, h=x8);
+    RAM512(in=in, out=y1, load=x1, address=address[3..11]);
+    RAM512(in=in, out=y2, load=x2, address=address[3..11]);
+    RAM512(in=in, out=y3, load=x3, address=address[3..11]);
+    RAM512(in=in, out=y4, load=x4, address=address[3..11]);
+    RAM512(in=in, out=y5, load=x5, address=address[3..11]);
+    RAM512(in=in, out=y6, load=x6, address=address[3..11]);
+    RAM512(in=in, out=y7, load=x7, address=address[3..11]);
+    RAM512(in=in, out=y8, load=x8, address=address[3..11]);
+    Mux8Way16(a=y1, b=y2, c=y3, d=y4, e=y5, f=y6, g=y7, h=y8, sel=address[0..2], out=out);
+}

Assignments/3_Sequential_Logic/RAM512.hdl

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+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/3/b/RAM512.hdl
+/**
+ * Memory of 512 16-bit registers.
+ * If load is asserted, the value of the register selected by
+ * address is set to in; Otherwise, the value does not change.
+ * The value of the selected register is emitted by out.
+ */
+CHIP RAM512 {
+    IN in[16], load, address[9];
+    OUT out[16];
+
+    PARTS:
+    DMux8Way(in=load, sel=address[0..2], a=x1, b=x2, c=x3, d=x4, e=x5, f=x6, g=x7, h=x8);
+    RAM64(in=in, out=y1, load=x1, address=address[3..8]);
+    RAM64(in=in, out=y2, load=x2, address=address[3..8]);
+    RAM64(in=in, out=y3, load=x3, address=address[3..8]);
+    RAM64(in=in, out=y4, load=x4, address=address[3..8]);
+    RAM64(in=in, out=y5, load=x5, address=address[3..8]);
+    RAM64(in=in, out=y6, load=x6, address=address[3..8]);
+    RAM64(in=in, out=y7, load=x7, address=address[3..8]);
+    RAM64(in=in, out=y8, load=x8, address=address[3..8]);
+    Mux8Way16(a=y1, b=y2, c=y3, d=y4, e=y5, f=y6, g=y7, h=y8, sel=address[0..2], out=out);
+}

Assignments/3_Sequential_Logic/RAM64.hdl

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+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/3/a/RAM64.hdl
+/**
+ * Memory of sixty four 16-bit registers.
+ * If load is asserted, the value of the register selected by
+ * address is set to in; Otherwise, the value does not change.
+ * The value of the selected register is emitted by out.
+ */
+CHIP RAM64 {
+    IN in[16], load, address[6];
+    OUT out[16];
+
+    PARTS:
+    DMux8Way(in=load, sel=address[0..2], a=x1, b=x2, c=x3, d=x4, e=x5, f=x6, g=x7, h=x8);
+    RAM8(in=in, out=y1, load=x1, address=address[3..5]);
+    RAM8(in=in, out=y2, load=x2, address=address[3..5]);
+    RAM8(in=in, out=y3, load=x3, address=address[3..5]);
+    RAM8(in=in, out=y4, load=x4, address=address[3..5]);
+    RAM8(in=in, out=y5, load=x5, address=address[3..5]);
+    RAM8(in=in, out=y6, load=x6, address=address[3..5]);
+    RAM8(in=in, out=y7, load=x7, address=address[3..5]);
+    RAM8(in=in, out=y8, load=x8, address=address[3..5]);
+    Mux8Way16(a=y1, b=y2, c=y3, d=y4, e=y5, f=y6, g=y7, h=y8, sel=address[0..2], out=out);
+}

Assignments/3_Sequential_Logic/RAM8.hdl

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+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/3/a/RAM8.hdl
+/**
+ * Memory of eight 16-bit registers.
+ * If load is asserted, the value of the register selected by
+ * address is set to in; Otherwise, the value does not change.
+ * The value of the selected register is emitted by out.
+ */
+CHIP RAM8 {
+    IN in[16], load, address[3];
+    OUT out[16];
+
+    PARTS:
+    DMux8Way(in=load, sel=address, a=x1, b=x2, c=x3, d=x4, e=x5, f=x6, g=x7, h=x8);
+    Register(in=in, out=y1, load=x1);
+    Register(in=in, out=y2, load=x2);
+    Register(in=in, out=y3, load=x3);
+    Register(in=in, out=y4, load=x4);
+    Register(in=in, out=y5, load=x5);
+    Register(in=in, out=y6, load=x6);
+    Register(in=in, out=y7, load=x7);
+    Register(in=in, out=y8, load=x8);
+    Mux8Way16(a=y1, b=y2, c=y3, d=y4, e=y5, f=y6, g=y7, h=y8, sel=address, out=out);
+}

Assignments/3_Sequential_Logic/Register.hdl

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+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/3/a/Register.hdl
+/**
+ * 16-bit register:
+ * If load is asserted, the register's value is set to in;
+ * Otherwise, the register maintains its current value:
+ * if (load(t)) out(t+1) = int(t), else out(t+1) = out(t)
+ */
+CHIP Register {
+    IN in[16], load;
+    OUT out[16];
+
+    PARTS:
+    Bit(in=in[0], out=out[0], load=load);
+    Bit(in=in[1], out=out[1], load=load);
+    Bit(in=in[2], out=out[2], load=load);
+    Bit(in=in[3], out=out[3], load=load);
+    Bit(in=in[4], out=out[4], load=load);
+    Bit(in=in[5], out=out[5], load=load);
+    Bit(in=in[6], out=out[6], load=load);
+    Bit(in=in[7], out=out[7], load=load);
+    Bit(in=in[8], out=out[8], load=load);
+    Bit(in=in[9], out=out[9], load=load);
+    Bit(in=in[10], out=out[10], load=load);
+    Bit(in=in[11], out=out[11], load=load);
+    Bit(in=in[12], out=out[12], load=load);
+    Bit(in=in[13], out=out[13], load=load);
+    Bit(in=in[14], out=out[14], load=load);
+    Bit(in=in[15], out=out[15], load=load);
+}

README.md

@@ -10,7 +10,8 @@
     > Реализация [NAND-логики](https://en.wikipedia.org/wiki/NAND_logic), то есть создание основных логических блоков (AND, OR, NOT, XOR, MUX, DMUX, а так же их версий для работы с 16-битной шиной) с помощью операции NAND ([И-НЕ или Штрих Шеффера](https://ru.wikipedia.org/wiki/Штрих_Шеффера))
 - [Project 2: Boolean Arithmetic](./Assignments/2_Boolean_Arithmetic/)
     > Создание [простого арифметико-логического устройства (ALU)](./Assignments/2_Boolean_Arithmetic/ALU.hdl) с помощью логических блоков из первого проекта, способного складывать и вычитать 16-битные числа
-- Project 3: Memory
+- [Project 3: Memory](./Assignments/3_Sequential_Logic/)
+    > Вводим единицу времени - такт, за счёт чего появляется текущее и следующее состояние, которое можно запоминать и изменять. Создаём простейшую память. На основе DFF компонента создаём [однобитный регистр](./Assignments/3_Sequential_Logic/Bit.hdl), затем [16-битный регистр](./Assignments/3_Sequential_Logic/Register.hdl), из них собираем блоки оперативной памяти ([RAM8](./Assignments/3_Sequential_Logic/RAM8.hdl), [RAM64](./Assignments/3_Sequential_Logic/RAM64.hdl), [RAM512](./Assignments/3_Sequential_Logic/RAM512.hdl), [RAM4K](./Assignments/3_Sequential_Logic/RAM4K.hdl), [RAM16K](./Assignments/3_Sequential_Logic/RAM16K.hdl)), а так же создаём простой [счётчик](./Assignments/3_Sequential_Logic/PC.hdl), который может использоваться для хранения текущей выполняемой инструкции и перехода к новой инструкции
 - Project 4: Machine Language
 - Project 5: Computer Architecture
 - Project 6: Assembler