Complete project 3

Assignments/3_Sequential_Logic/Register.hdl

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+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/3/a/Register.hdl
+/**
+ * 16-bit register:
+ * If load is asserted, the register's value is set to in;
+ * Otherwise, the register maintains its current value:
+ * if (load(t)) out(t+1) = int(t), else out(t+1) = out(t)
+ */
+CHIP Register {
+    IN in[16], load;
+    OUT out[16];
+
+    PARTS:
+    Bit(in=in[0], out=out[0], load=load);
+    Bit(in=in[1], out=out[1], load=load);
+    Bit(in=in[2], out=out[2], load=load);
+    Bit(in=in[3], out=out[3], load=load);
+    Bit(in=in[4], out=out[4], load=load);
+    Bit(in=in[5], out=out[5], load=load);
+    Bit(in=in[6], out=out[6], load=load);
+    Bit(in=in[7], out=out[7], load=load);
+    Bit(in=in[8], out=out[8], load=load);
+    Bit(in=in[9], out=out[9], load=load);
+    Bit(in=in[10], out=out[10], load=load);
+    Bit(in=in[11], out=out[11], load=load);
+    Bit(in=in[12], out=out[12], load=load);
+    Bit(in=in[13], out=out[13], load=load);
+    Bit(in=in[14], out=out[14], load=load);
+    Bit(in=in[15], out=out[15], load=load);
+}